1. Field of the Invention
The present invention relates to a bit line sensing amplifier driving/controlling circuit, specifically, to a circuit for rapidly supplying pull up/down voltages to a bit line sensing amplifier, thereby reducing power consumption.
2. Discussion of Related Art
As illustrated in FIG. 1, in semiconductor devices, a memory includes a cell array CA for storing data and a bit line sensing amplifier array BSAA for amplifying the data of the cell array CA.
In the memory cell array CA, the data cells C are arranged in a N.times.M matrix. Each cell is connected to a word line WL and a bit line BL. The even cells are connected to one bit line BL (BL1) and the odd cells are connected with an associated bit line (/BL1). Where the cells in the cell array CA are arranged in an N.times.M matrix, the cell array CA has M word lines, WL1 through WLM. There is a pair of bit lines in every column. Therefore, n pairs of bit lines, BL1 and /BL1 through BLN and /BLN, form the cell memory.
A bit line sensing amplifier array BSAA, made of n bit line sensing amplifiers BSA1 to BSAN, is connected to CA. Each of the sensing amplifiers is connected to a pair of bit lines (BL:/BL) to amplify the potential difference (voltage) between the two bit lines, thus sensing data held in the cell. These sensing amplifiers comprise pull-up devices made of first and PMOS transistors P1 and P2, connected in series with pull-down devices, made of first and second NMOS transistors M1 and M2, between the first and second driving lines SPC and SNCB. The gates of the first and second PMOS transistors P1 and P2 being connected to the first and second bit lines BL and /BL, respectively, and the gates of the first and second NMOS transistors M1 and M2 being connected to the first and second bit lines /BL and BL, respectively.
A bit line driver BLD is connected to the bit line sensing amplifier array BSAA through driving lines SPC and SNCB, thus supplying the voltage for driving the bit line sensing amplifiers BSA1 to BSAN. The PMOS transistors serving as the pull-up devices for the sensing amplifiers are commonly connected to the first driving line SPC of the bit line driver BLD, and the NMOS transistors serving as the pull-down devices are connected to the second driving line SNCB of the bit line driver. The bit line driver BLD applies a positive operational voltage VCC to the first driving line SPC and grounds the second driving line SNCB according to a control signal generated by the bit line controller BLC.
The operation of the previously described driving/controlling circuit, as illustrated in FIG. 1, will be described with reference to FIG. 3.
When high state voltage data is stored in a cell in the memory cell array, the bit line /BL, which is paired with another bit line BL connected to the cell C and is preset to a voltage which is of a half potential level (VBLP), receives a driving voltage applied to the word line connected to the cell. When this occurs, a pass transistor MC corresponding to cell C is turned on and the charge in a capacitor CAP is discharged to bit line BL1. In other words, a charge redistribution occurs. The potential of the bit line BL preset to VBLP differs from the potential of the bit line /BL, to which the charge of the capacitor CAP is applied and produces a potential difference .DELTA.V between the two bit lines. Thus the bit line driver BLD applies VCC to the first driving line SPC and VSS (i.e., ground) to the second driving line SNCB.
As illustrated in FIG. 3, when the potential of BL1 is increased and the potential of /BL1 is decreased so that the data stored in capacitor CAP is read through the data bus connected to the sensing amplifier; the same data can be stored in the cell. Thus, if the driving voltage is applied to the sensing amplifier, the voltage Vgs between the gate and the source of the second NMOS transistor M2, serving as a pull-down transistor in the sensing amplifier and connected to the second driving line SNCB, is higher than the Vgs of the first NMOS transistor M1 by .DELTA.V. Therefore, the second NMOS transistor M2 is turned on before the first NMOS transistor M1, and the charge of the second bit line /BL1 is discharged before first bit line BL1. Accordingly, the vgs value of the first NMOS transistor M1 is decreased and the discharge path of the first bit line BL1 is cut off.
In contrast, the PMOS transistor serving as the pull-up device for the sensing amplifier operates as follows.
As the Vsg of the first PMOS transistor P1, whose gate is connected to the first bit line BL1, is higher than that of the second PMOS transistor P2, whose gate is connected with the second bit line /BL1, the first PMOS transistor P1 is turned on earlier. Consequently, the first bit line /BL1 is pulled up and the discharge current path is cut off. The pull-up transistor P2 is turned off and cuts off the supply of positive voltage to the bit line /BL1. The positive voltage VCC is applied to the bit line BL1, thereby increasing the bit line BL1 voltage to a predetermined level.
FIG. 2 illustrates an example embodiment of the sensing amplifier driving/controlling circuit which has the bit line driver BLD for a driving the bit line sensing amplifier, and the controller BLC.
The conventional sensing amplifier driving/controlling circuit has a voltage generator 1 for generating a predetermined reference voltage VREF; a comparator 2 having a non-inverse data input terminal + for a receiving reference voltage generated by voltage generator 1, and an inverse data input terminal -, connected to the first driving line SPC, to thereby compare the two signals; NAND gate 3 for receiving an output signal of the comparator 2 and a control signal SN, that is externally input, to perform a NAND operation on the two signals; an NMOS transistor MN5 that turns on or off according to the control signal and selectively connects the second driving line SNCB to the ground voltage; and a PMOS transistor MP4 that turns on or off according to the output of the NAND gate 3 and selectively connects the positive voltage VCC to the first driving line SPC.
With reference to FIG. 3, the operation of the described sensing amplifier driving/controlling circuit is described below.
After the word line WL is enabled, when the control signal SN of the bit line sensing amplifier BSAA is converted from a low state into a high state, the NMOS transistor MN5 is turned on so that the potential of the second driving line SNCB, which is charged at 1/2 VCC as well as the bit line; is discharged and reduced to the ground voltage. Furthermore, as the output signal of comparator 2 is in a high state, because the output voltage of the voltage generator 1 is set higher than the 1/2 VCC, the output of the NAND gate becomes high when the control signal SN is in a low state. If the control signal is switched from a low state to a high state, the output of the NAND gate changes from the high state to the low state, thereby turning on PMOS transistor 4. Accordingly, as the PMOS transistor 4 is turned on, positive voltage VCC is applied to first driving line SPC, pulling up the first driving line SPC from the 1/2 VCC state to the VCC state.
In this way, the voltage applied to the first driving line SPC is input to the inverse data input terminal - of the comparator 2. Comparator 2 compares it to the reference voltage VREF, applied through its non-inverse data input terminal +, and if it is higher than reference voltage VREF, comparator 2 applies the low state signal to one input terminal of the NAND gate NAND 3, converting the output of the NAND gate 3 into the high state. Consequently, PMOS transistor 4 is turned off, cutting off the VCC supply to the first driving line SPC. The voltage of the reference voltage VREF is determined by the expected voltage of the first driving line SPC, and is generally set to a level suitable for being restored in the cell similar to the level of the positive voltage VCC.
As illustrated in FIG. 3, the voltage applied to the first driving line SPC oscillates continuously because the voltage is controlled by the output of the comparator 2 while the control signal SN is in a high state.
The technique for driving/controlling the bit line of the described conventional driving/controlling sensing amplifier has a problem with consuming excessive power because the comparator 2 is always in the active state.
To overcome the problems with the conventional sensing amplifier driving/controlling circuit resulting in excessive power consumption, a technique described in U.S. Pat. No. 5,258,950 has been developed. The technique employs the circuit of FIG. 4. The operation of the circuit is described below with reference to FIG. 5.
After a word line WL is enabled, and if a control signal SN of a bit line sensing amplifier BSAA is switched from low to high, an NMOS transistor 41, is turned on and discharges the second driving line SNCB to the ground voltage.
The control signal SN becomes low after passing through a second inverter 42, and is applied to the gate of a second PMOS transistor 43 to turn on the transistor. Accordingly, the internal voltage VDD is applied to the first driving line SPC. Furthermore, the control signal SN changes from high to low by passing through a pulse generator SP1 and a latch circuit having first and second NAND gates NAND1 and NAND2, and therefore is used for turning on the first PMOS transistor 44. The first driving line SPC is pulled up rapidly with the internal voltage VDD and the external voltage VCC by turning on the first and second PMOS transistors 44 and 43.
The voltage pulled up in the first driving line SPC becomes higher than the reference voltage and similar to the internal voltage VDD. Thus, the VREF voltage is set lower than the external voltage VCC and higher than the internal voltage VDD. Under these conditions, a current mirror typed comparator 45 changes the voltage of the output line connected to a short low pulse generator 46, where the first driving line SPC is at a VDD level, to generate a short low pulse using short low pulse generator 46, the pulse to the second NAND gate NAND2. In accordance with this, the signal input to the gate of the first PMOS transistor 44 becomes high.
At the initial stage of the operation, the first and second PMOS transistors 44 and 43, respectively connecting the external voltage VCC to the first driving line and the internal voltage VDD to the second driving line, operate at the same time. If the voltage applied to the first driving line SPC is higher than the reference voltage VREF, only the second PMOS transistor 43, operating with the internal voltage VDD, is continuously in the "ON" state, and the first PMOS transistor 44, for supplying the external voltage VCC to the first driving line SPC, is turned off to thereby reduce power consumption while maintaining the voltage of the first driving line SPC. The first PMOS transistor 44, supplying the external voltage VCC to the first driving line SPC, is turned off to reduce power consumption, thus maintaining the voltage level of the first driving line.
FIG. 5 illustrates the wave form of the voltage applied to each signal line when operating the sensing amplifier driving/controlling circuit.
To solve the problem of the conventional art, the circuit is designed to operate the comparator 45 only during an initial stage of the pull-up operation. As the first driving line SPC is not a simple passive device, as illustrated in FIG. 5, the voltage of the first driving line SPC is drastically decreased when the first PMOS transistor 44 is turned off, thus its wave form is peak-shaped. Consequently, even though the power consumption is reduced, it takes too much time to pull up the first driving line SPC to a stable internal voltage VDD level.
Additionally, if the voltage applied to the first driving line SPC is not higher than the reference voltage VREF while the bit line sensing amplifier BSAA is enabled, output from the latch circuit is not converted even though the enable signal SN is reset. As the output signal of the first inverter maintains the low state, excessive power consumption results. Furthermore, the construction of the latch circuit may be complex.
With memory devices a burn-in test is performed under conditions of high-voltage and high-temperature to detect devices having poor reliability. Here, the external high voltage directly applied to the cell inside the chip through the VCC line may damage the devices.